The present invention relates generally to integrated circuits, and more particularly to techniques for designing integrated circuits.
In an integrated circuit (IC), signals are transferred between different pairs of sequential circuit elements, e.g., from a transmitting (a.k.a. launch) flip-flop to a receiving (a.k.a. capture) flip-flop. In order to operate properly, each signal transfer between each pair of sequential circuit elements must be completed within one clock cycle.
Slack refers to the difference between the required time and the arrival time, e.g., the difference between a clock cycle and the time taken during a signal transfer from a launch element to a capture element. In a valid IC design, each signal transfer path has slack that is either positive (indicating that the signal transfer duration is shorter than one clock cycle) or zero (indicating that the signal transfer duration is equal to one clock cycle). If one or more signal paths in an IC design have negative slack (indicating that the signal transfer duration is greater than one clock cycle), then those signal paths are referred to as failing paths, and the IC design is invalid.
Increasing market demands for high performance and low power in SoC (System on Chip) integrated circuits places a lot of focus on design-optimization techniques from synthesis through design closure. Synthesis techniques play a vital role in the choice of data path operators and gate-level optimization. With shrinking design cycles, this necessitates that synthesis tools give best QoR (Quality of Results) in terms of performance and power with minimum iterations.
In some design scenarios, top failing paths cannot be optimized further because of constraints not being mature (e.g., due to the design being in an initial phase) or design architectural issues. In such cases, the synthesis engine may leave many sub-optimal paths (paths not fully optimized) beneath the top failing paths. EDA (Electronic Design Automation) algorithms are presently coded to put high effort on the top failing paths, while the paths below them get a very low weight/effort. This can result in (i) multiple iterations between the physical implementation team and the STA (Static Timing Analysis) team and (ii) a lot of sub-optimal paths in the design. The problem is seen across SoCs with no effective solution available from the EDA industry so far.
FIG. 1 shows a high-level block/flow diagram of a conventional technique for designing an integrated circuit. In step 106, the RTL (Register Transfer Level) 102 and Lib (Library) 104 information are stitched together where the top-level design and its references are resolved. Also, during this step, data structures, based on top-level design references, are built, and the semantics of the RTL files are verified as well. The RTL and Lib databases contain the timing information of the technology cells that are used during synthesis.
In step 108, timing and design constraints are specified for the IC. In step 110, a synthesis engine is used to generate a current design for the IC. In step 112, it is determined whether the current IC design meets the timing constraints specified in step 108, including whether each signal transfer path in the current IC design has either positive or zero slack. If so, then the current IC design is valid, and the process continues to step 116, where a gate-level netlist for Placement and Routing (PnR) is generated for the current IC design.
If, however, step 112 determines that one or more of the signal transfer paths in the current IC design have negative slack, then processing returns to step 108 to modify the constraints for another iteration of the technology mapping of step 110. In some situations, the number of iterations of steps 108, 110, and 112 can become large without ever being able to generate a valid IC design. Accordingly, it would be advantageous to be able to move to the PnR step without an excessive number of iterations to address timing issues.